In general, the signal-to-noise ratio (SNR) is a measure of signal strength relative to background noise. As applied to a frequency-to-digital converter (FDC), the SNR relates to the amount of noise introduced during the digital conversion process. Maximizing the SNR is a desired design consideration.
A conventional FDC receives a hard-limited sine-wave input signal, counts the edge transitions in the signal for a given period of time, and compares the result with a reference clock signal to obtain the frequency of the input signal. The input signal frequency is then converted to a corresponding digital number. Typically, the FDC determines the input signal frequency using the relationship between the ratio of the input signal frequency to the reference clock frequency, and the ratio of the number of rising and falling edges of the input signal to the number of rising and falling edges of the reference clock signal. Since the reference clock frequency and the number of rising and falling edges of the reference clock signal are known, and the number of rising and falling edges of the input signal are counted by the FDC, the input signal frequency is calculated using the above relationship. The phase change between each rising edge is 360 degrees, and the phase change between each successive rising edge and falling edge is 180 degrees. As such, this procedure can only differentiate the signal with 180 degrees phase change.
A digital conversion circuit includes a FDC. In many applications, the digital conversion circuit is configured as a phase-locked loop (PLL) or a frequency-locked loop (FLL).
FIG. 1 illustrates an exemplary digital conversion circuit configured as a FLL. The digital conversion circuit 2 includes a frequency detector 4, a loop filter 6, and a voltage controlled oscillator (VCO) 8 coupled as a frequency-locked loop. The frequency detector 4 includes a frequency-to-digital comparator (not shown). The VCO 8 includes an oscillator 12 and a dividing circuit 14, which in this exemplary configuration is a divide by 2 circuit. The oscillator 12 provides a source signal to the divide by 2 circuit 14. The divide by 2 circuit 14 divides down the frequency of the received source signal and outputs two divided down signals, a first signal and a second signal. The first signal and the second signal have a frequency that is one-half that of the frequency of the source signal. The first signal and the second signal have the same waveform, but the second signal is phase-shifted by 90 degrees relative to the first signal.
The divide by 2 circuit 14 is coupled to the frequency detector 4 such that the first signal is provided as feedback to lock the FLL. The first signal is used as an input signal by the frequency detector 4, which in turn converts the first signal to a corresponding digital word. The digital word is provided as input to the oscillator 12 via the loop filter 6.
A typical oscillator generates a source signal with a frequency in a range about 4 GHz. In a high band application, a single divide by 2 circuit is used to divide down the source signal to form the first signal and the second signal, each with a frequency of about 2 GHz. In a high band application, the first signal with the divided down frequency is output from the digital conversion circuit 2. In a low band application, an additional divide by 2 circuit is used to further divide down the first signal to form two additional signals, each with a frequency of about 1 GHz. In either application, using only a single divided down signal as feedback to the frequency detector 4 results in a decreased SNR. In the high band application, the SNR of the output signal decreases by about 6 dB. In the low band application, the SNR of the output signal decreases by about 12 dB.